A flash memory device is a nonvolatile memory device that does not lose data stored therein even if power is turned off. In addition, the flash memory can record, read, and delete data at a relatively high speed.
Accordingly, the flash memory device is widely used for the Bios of a personal computer (PC), a set-top box, a printer, and a network server in order to store data. Recently, the flash memory device is extensively used for digital cameras and portable phones.
In such a flash memory device, a semiconductor device having a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) structure is often used.
Different from a flash memory device having a floating gate including polycrystalline silicon, the SONOS memory device is a charge-trap type device, in which gate voltage is applied so that charges (electrons) pass through a thin oxide layer formed on silicon to become injected into or released from a charge trap formed in a silicon nitride layer.
FIGS. 1A to 1C are sectional views showing the procedure for manufacturing flash memory devices according to related art.
As shown in FIG. 1A, when a split select gate is defined by a photo and etch process, select gate lengths of cells may be different from each other (L1≠L2) due to an overlay misalign in the photo process, so one cell (A-Cell shown on the left) may have characteristics different from characteristics of the other cell (B-Cell shown in the right).
In addition, as shown in FIG. 1B, when the split select gate is defined by the photo and etch process in a state in which a local nitride layer is used as a memory site, the cells may have various nitride lengths (L3≠L4) and select gate lengths (L1≠L2) due to the critical dimension CD variation and overlay misalign in the photo process, so that characteristic variation of the left cell (A-Cell) and the right cell (B-Cell) may be increased.
Further, referring to FIG. 1C, it can be difficult to remove polysilicon covering a source region between adjacent cells without damage when forming an active gate poly and a memory gate poly.